A well-thought-out layout design is crucial for improving efficiency, reducing thermal stress, and minimizing the impact of noise between traces and components. This is because the designer needs to fully understand the path of current conduction and the flow of signals within the electrical system. Ideally, when a prototype power board is first introduced, it should not only function properly but also operate quietly with minimal heat generation. However, this scenario is quite rare.
One common issue encountered in switching power supplies is an “unstable†switching waveform. In some cases, fluctuations in the magnetic components can produce audible noise. If the root cause lies in the PCB layout, it can be challenging to pinpoint. Thus, getting the PCB layout right from the start of the design process for a switching power supply is vital.
Power supply designers need a comprehensive understanding of both technical details and the functional requirements of the final product. Therefore, from the very beginning of the board design project, the source designer should collaborate closely with the PCB layout designer on critical electrical layouts.
An effective layout design enhances power efficiency, reduces thermal stress, and most importantly, minimizes noise and interactions between traces and components. To achieve these objectives, designers must grasp the current conduction paths and signal flows within the switching power supply. Keeping these design principles in mind is essential for achieving the correct layout in non-isolated switching power supplies.
### Planning the Layout
For an embedded DC/DC power supply on a larger board, placing the power supply output close to the load device is ideal for optimal voltage regulation, load transient response, and system efficiency. This placement helps minimize interconnect impedance and voltage drop on the PCB traces. Ensuring good airflow and limiting thermal stress is equally important; if forced air cooling is used, the power supply should be positioned close to the fan.
Large passive components like inductors and electrolytic capacitors should not obstruct airflow around low-profile semiconductor components such as power MOSFETs or PWM controllers. Sensitive signal lines should ideally avoid being placed directly beneath the power supply; otherwise, an internal ground plane should be placed between the power supply layer and the small signal layer for shielding purposes.
The key is to plan the location of the power supply and the necessary board space during the early design and planning stages of the system. Often, designers overlook this advice and focus instead on what they perceive as more “important†or “exciting†circuits on large system boards. Power management is sometimes treated as an afterthought, with power components squeezed into any available extra space on the board. This approach can hinder efficient and reliable power supply design.
For multi-layer boards, a good practice is to place a DC or DC input/output voltage layer between the high current power component layer and the sensitive small signal trace layer. This formation acts as a DC voltage layer, providing an AC ground to shield small signal traces from high noise power traces and components.
In general, the ground plane or DC voltage layer of a multi-layer PCB should remain continuous. If separation is unavoidable, the number and length of traces on these layers should be minimized, and their routing should follow the same direction as the large current to mitigate the effects.
Figures 1a and 1c illustrate poor layer structures in a six-layer and four-layer switching power supply PCB, respectively. These structures sandwich the small signal layer between the high current power layer and the ground plane, thereby increasing capacitive noise coupling between the high current/voltage power layer and the analog small signal layer.
Figures 1b and 1d show better layer configurations for six-layer and four-layer PCB designs, respectively, helping to minimize interlayer coupling noise while using the formation to shield small signal layers. The main takeaway is: always place a ground plane next to the outer power level layer. Use thick copper foil for the external high-current power layer to minimize PCB conduction loss and thermal resistance.
### Power Level Layout
The switching power supply circuit can be divided into two main parts: the power stage circuit and the small signal control circuit. The power stage circuit contains components responsible for transmitting large currents. Generally, these components are placed first, followed by the placement of the small signal control circuits at specific points in the layout.
High current traces should be short and wide to minimize PCB inductance, resistance, and voltage drop. This is particularly important for traces with high di/dt pulse currents.
Figure 2 shows the continuous current path and pulse current path in a synchronous buck converter. The solid line represents the continuous current path, while the dashed line represents the pulse (switch) current path. The pulse current path includes traces connected to the following components: an input decoupling ceramic capacitor CHF; an upper control FET QT; and a lower synchronous FET QB, along with an optional parallel Schottky diode.
Figure 3a demonstrates the PCB parasitic inductance in a high di/dt current path. Due to the parasitic inductance, the pulsed current path not only radiates magnetic fields but also generates large voltage ringing and spikes on the PCB traces and MOSFETs. To minimize PCB inductance, the pulse current loop (commonly referred to as the thermal circuit) should have the smallest possible circumference when laid out, with its traces being short and wide.
The high-frequency decoupling capacitor CHF should be a 0.1μF~10μF, X5R or X7R dielectric ceramic capacitor with very low ESL (effective series inductance) and ESR (equivalent series resistance). Larger capacitive dielectrics (such as Y5V) may experience significant drops in capacitance values at varying voltages and temperatures, making them unsuitable for CHF.
Figure 3b provides a layout example for the critical pulse current loop in a buck converter. To limit voltage drop and the number of vias, the power components are placed on the same side of the board, and the power traces are also placed on the same layer. When a power line needs to be moved to another layer, select a trace in the continuous current path. When using vias to connect PCB layers in high current loops, multiple vias should be used to minimize impedance.
Figure 4 shows the continuous current loop and pulse current loop in the boost converter. At this stage, the high-frequency ceramic capacitor CHF should be placed near the output of MOSFET QB and the boost diode D.
Figure 5 is a layout example of a pulse current loop in a boost converter. Here, the key is to minimize the loop formed by the switching transistor QB, the rectifier diode D, and the high-frequency output capacitor CHF.
Figure 5, this figure shows the thermal loop and parasitic PCB inductance (a) in the boost converter; the recommended layout (b) to reduce the thermal loop area.
Figures 6 and 7 (omitted) provide an example of a synchronous buck circuit emphasizing the importance of decoupling capacitors. Figure 6a shows a two-phase 12VIN, 2.5VOUT/30A (max) synchronous buck power supply using the LTC3729 dual-phase single VOUT controller IC. At no load, the switching node SW1 and SW2 waveforms and output inductor current are all stable (Figure 6b). However, if the load current exceeds 13A, the waveform of the SW1 node begins to lose its periodicity. When the load current is higher, the problem worsens (Figure 6c).
This issue can be resolved by adding two 1μF high-frequency ceramic capacitors to the input of each channel. These capacitors isolate and minimize the thermal loop area of each channel. Even at maximum load currents up to 30A, the switching waveform remains stable.
### High DV/DT Switch Area
In Figures 2 and 4, the SW voltage swing between VIN (or VOUT) and ground has a high dv/dt rate. This node is rich in high-frequency noise components and is a potent source of EMI noise. To minimize coupling capacitance between the switch junction and other noise-sensitive traces, the SW copper area should be made as small as possible. However, to handle large inductor currents and provide a heat sink for the power MOSFET, the PCB area of the SW junction cannot be overly reduced. It is generally recommended to place a grounded copper foil area under the switch junction to provide additional shielding.
If there is no heat sink designed for surface-mount power MOSFETs and inductors, the copper foil area must have sufficient heat sink area. For DC voltage junctions (such as input/output voltage and power ground), a reasonable approach is to make the copper foil area as large as possible.
Multiple vias help further reduce thermal stress. To determine the appropriate copper area for a high dv/dt switch junction, a design balance must be struck between minimizing dv/dt-related noise and providing good MOSFET heat dissipation.
### Control Circuit Layout
Keep the control circuit away from the high-noise switch copper foil area. For a buck converter, a good strategy is to place the control circuit close to the VOUT+ terminal, while for a boost converter, the control circuit should be close to the VIN+ terminal, allowing the power traces to carry continuous current.
If space permits, there should be a small distance (0.5" to 1") between the control IC and the power MOSFET and inductor (both high-noise and high-heat components). If space is limited and the controller must be placed close to the power MOSFET and inductor, pay particular attention to the ground or ground traces to isolate the control circuitry from the power components.
The control circuit should have an independent signal (analog) ground different from the power level. If there are separate SGND (signal ground) and PGND (power ground) pins on the controller IC, they should be routed separately. For control ICs with integrated MOSFET drivers, the small signal portion of the IC pin should use SGND.
Only one connection point is needed between the signal ground and the power ground. A reasonable approach is to return the signal ground to a clean point in the power formation. Two types of ground can be achieved by connecting only two grounding traces under the controller IC.
This pad should be soldered to the PCB to minimize electrical impedance and thermal resistance. Multiple vias should be placed in the ground pad area.
### Loop Area and Crosstalk
Two or more adjacent conductors can create capacitive coupling. The high dv/dt on one conductor couples current through the parasitic capacitance on the other conductor. To reduce the coupling noise of the power stage to the control circuit, the high-noise switching traces should be kept away from sensitive small signal traces. If possible, place the high-noise traces and sensitive traces on separate layers and use the internal ground plane as a noise shield.
Space permitting, the control IC should be placed a small distance (0.5" to 1") from the power MOSFET and inductor, which are both noisy and hot.
### Trace Width Selection
The specific controller pins, current levels, and noise sensitivity vary, so specific trace widths must be chosen for different signals. Typically, small signal networks can be narrower, with traces from 10mil to 15mil wide. The high current network (gate drive, VCC, and PGND) should be wider, and the specific width is defined by the current.
In conclusion, a well-designed layout is essential for efficient and reliable power supply operation. Proper planning, attention to detail, and collaboration between designers are key to achieving optimal performance.
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