74ls164 function and working principle

74ls164 function

The 74ls164 is an 8-bit edge-triggered shift register, so its function is obviously serial input data and 8-bit parallel output.

Data is serially input through one of two inputs (DSA or DSB); either input can be used as a high level enable to control the data input of the other input. The two inputs are either connected together or the unused inputs are tied high and must not be left floating.


74ls164 function truth table

How 74ls164 works

74ls164 internal circuit diagram

The 8-bit shift register features an AND gate enable control serial input and an asynchronous reset input. The enable control input can control unwanted input data signals to a low level. When the reset signal is low, the output is low regardless of the state of other signals; when the reset signal is high, the register shifts the input data sequentially from the first bit on the rising edge of each clock signal. .

74ls164 workflow

74ls164 logical symbol

Each time the clock (CP) goes from low to high, the data is shifted to the right by one bit and input to Q0. Q0 is the logical AND of the two data inputs (DSA and DSB), which will hold the length of the setup time before rising the clock edge. .

A low level on the main reset (MR) input will disable all other inputs, clearing the registers asynchronously, forcing all outputs low.


74ls164 logic diagram

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