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System design based on FPGA and high speed A/D converter chip ADC08D1500

Abstract: To simultaneously calculate the correlation of four Stokes vector parameters and retrieve the sea surface wind field, a novel digital correlator design is introduced. This method integrates high-speed digital correlators used in digital polarimeters, along with advanced data sampling and processing systems. Four high-speed ADCs (ADC08D1500) are employed to sample four signals concurrently. The sampled data is processed using Xilinx’s next-generation FPGA, the Virtex5 chip. The correlated results are then transferred to a computer via a serial port. The system architecture includes detailed interface circuitry and timing control design for each component. It is capable of calculating correlations at a sampling rate of up to 1.5 GHz for four signals.

0 Preface

Studying ocean surface winds plays a crucial role in meteorology, oceanography, and climatology. A key feature of full-polarization radiometers is the use of multi-path correlation techniques to correlate horizontal and vertical polarization signals, generating parameters necessary for retrieving the sea surface wind field model. The modified Stokes vector can describe the second-order statistical properties of the radiation field in space. The elements in this vector are expressed in terms of brightness temperature K, as shown in the following equation.

Wideband digital correlator design based on high speed ADC and FPGA

Four Stokes parameters can be derived by correlating the vertical and horizontal polarization signals. Most current polarized radiometers rely on analog correlators. However, as the demand for accurate wind field measurements increases, analog devices have become insufficient. A digital polarized radiometer uses a digital correlator to perform autocorrelation and cross-correlation between two polarized channels. Compared to their analog counterparts, digital correlators offer greater flexibility through VLSI technology, enabling full parallel wideband correlation. These systems first sample the analog signal and then quantize it for correlation. According to Nyquist's theorem, the sampling frequency must be at least twice the signal bandwidth to avoid information loss. This necessitates high-frequency sampling circuits, which impose strict requirements on accuracy and reliability. This paper presents a high-frequency, high-reliability signal sampling and correlation system. The system employs the NS ADC08D1500, known for its high precision and low power consumption, operating at a maximum sampling rate of 1.5 GHz. The FPGA, with its compact size, high integration, and low power consumption, serves as the core for data reception and correlation calculations.

1 Digital Correlator Design

In the signal acquisition module, two ADC08D1500 chips simultaneously sample four signals. The ADC outputs are in LVDS format, with a 32-bit width per channel, and are provided in parallel. The Xilinx Virtex5 FPGA is used to receive and process the output from both ADCs. Additionally, the FPGA controls the reset function of the ADCs, ensuring they operate in sync. For clock synchronization, the AD9514 high-speed clock driver is used to provide phase-aligned sampling clocks to both ADCs. The correlation results computed by the FPGA are transmitted to the PC through a serial port. The system block diagram is illustrated in Figure 1.

Figure 1 system structure framework

2 ADC and Peripheral Circuit 2.1 ADC

The system utilizes two ADC08D1500 chips. National Semiconductor’s ADC08D1500 is a high-performance ADC with a typical power consumption of 1.9W. Each channel operates at a sampling rate of 1.5 GHz, with 8-bit resolution and a full power bandwidth of 1.7 GHz. The input peak-to-peak voltage is set to 870 mV through pin configuration. After 2^31 sample clock cycles, the ADC automatically calibrates itself.

DCLK is used to latch the data sent to an external device. It operates in DDR mode, and the ADC internally performs a 1:2 demux, dividing the output clock by two relative to the sampling clock. This reduces the clock frequency entering the FPGA to one-quarter of the sampling rate, simplifying high-speed correlation processing. The OR pin indicates if the input is out of range. It is connected to the FPGA and drives external LEDs. Figure 2 shows the functional block diagram of the ADC.

Figure 2 ADC08D1500 Functional Framework

2.2 Clock Control

The ADC08D1500 requires a differential clock input. The sampling clocks for the two ADCs must be strictly synchronized to ensure amplitude and phase consistency. In this design, the AD9514 clock driver generates two in-phase differential clocks. The AD9514 accepts LVPECL or LVDS inputs and outputs in LVPECL, LVDS, or CMOS levels. Two LVPECL outputs are ac-coupled to the ADCs, with a maximum output frequency of 1.6 GHz. Figure 3 illustrates the LVPECL output termination circuit.

Figure 3 LVPECL output termination circuit

2.3 ADC Reset

Synchronous resetting of the two ADCs ensures they operate in sync. The DCLK_RST pin is used for resetting the ADC. A positive pulse can reset and synchronize the DCLK outputs of multiple ADCs. The reset signal must remain active for more than four sample clock cycles. As shown in Figure 4, trpw must be at least four sample clock cycles. The FPGA controls the DCLK_RST pin to implement simultaneous resets of the two ADCs. The recovery time Tad is 3.5 ns.

Figure 4 DCLK_RST reset timing

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