Electronic engineers come to see these 29 mistakes, have you ever committed?
Don't assume that the "bug-free forever" program is something that only engineers who love to make mistakes would pursue. The electronic lion of innovation is no exception! The key point is that often, engineers don’t realize they are making mistakes. Instead, they believe they’ve found a better solution and feel excited about it.
When dealing with a large number of components and complex circuit diagrams, it's inevitable that small errors occur from time to time. Sometimes, these mistakes can lead to the discovery of something entirely new — which could position you as a pioneer in the next technological revolution!
For junior engineers, learning from the experiences of seasoned professionals can be incredibly valuable. If you've been tripped up by similar issues before, it’s wise to avoid repeating them. Take a moment to check if any of these 29 common mistakes sound familiar to you. Have you made them?
[Image: http://i.bosscdn.com/blog/o4/YB/AF/qtxWSAPxLxAACGLh4meNo525.png]
**Mistake 1: Cost Savings**
**Common Error:** What color should the indicator on the panel be? I like blue, so I'll go with that.
**Solution:** Indicator lights in red, green, yellow, and orange have been around for decades and are well-established in terms of cost and availability, usually under 5 cents. Blue LEDs, on the other hand, are relatively new and less mature, costing four to five times more. Unless there's a specific need (like video signals), it's best to avoid blue unless absolutely necessary.
**Common Error:** The value of pull-up/pull-down resistors doesn’t matter much, so I’ll just use 5K.
**Solution:** There’s no 5K resistor in standard production. The closest options are 4.99K (1% tolerance) or 5.1K (5% tolerance), which are significantly more expensive than 4.7K (20% tolerance). Using non-standard values increases cost and may affect performance. It's better to stick to standard values unless precision is critical.
**Common Error:** Why not use a CPLD instead of 74XX gates? It looks more advanced.
**Solution:** 74XX logic gates are cheap, while CPLDs are costly and add unnecessary complexity. They require more design effort and documentation, which can slow down production. For most applications, 74XX parts offer better cost-performance without sacrificing functionality.
**Common Error:** The PCB design isn’t complicated, so I’ll just use thin traces and auto-route.
**Solution:** Auto-routing uses more board space and increases manufacturing costs. Factors like trace width, via count, and board area all impact pricing. Manual routing is more efficient and cost-effective, especially for mass production.
**Common Error:** Our system needs the fastest chips possible, including the fastest MEM, CPU, and FPGA.
**Solution:** Not every component needs to be the fastest. Increasing speed often doubles the cost and can negatively impact signal integrity. Choose components based on actual performance requirements rather than just speed.
**Common Error:** As long as the program works, efficiency doesn’t matter.
**Solution:** Efficient code saves money on hardware—like using a slower CPU or smaller memory. This is especially true for FPGA and CPLD designs, where optimization can drastically reduce costs.
[Image: http://i.bosscdn.com/blog/o4/YB/AF/qtxWSABAN2AABq6QhTyRc746.png]
**Mistake 2: Reliability Design**
**Common Error:** We tested the board and didn’t find any issues, so we don’t need to check the chip manual.
**Solution:** Always follow the manufacturer’s specifications. Even if your board passes tests now, changes in production or parameters could cause problems later. Relying on the manual ensures long-term reliability.
**Common Error:** It’s not my fault if the user makes an error.
**Solution:** Users will make mistakes, so your design must anticipate and protect against them. Implement safeguards to prevent damage from incorrect operations.
**Common Error:** If the other side has a problem, it’s not my issue.
**Solution:** Ensure your design is compatible with various external interfaces. Don’t let one faulty connection bring down the entire system. Your design should remain functional even when other components fail.
**Common Error:** If software controls this part, it should be error-free.
**Solution:** Software can be unreliable. Design your hardware to prevent permanent damage, even if the software fails.
[Image: http://i.bosscdn.com/blog/o4/YB/AF/qtxWSAct_oAAD1k9-Kl38721.png]
**Mistake 3: System Efficiency**
**Common Error:** Interrupts are faster than polling.
**Solution:** While interrupts are real-time, too many can cause system instability. Polling can be more efficient in some cases, but combining both (interrupt-driven polling) offers the best of both worlds.
**Common Error:** A 200MHz CPU is better than a 100MHz one.
**Solution:** CPU speed alone doesn’t determine performance. Memory bandwidth and other factors can be the real bottleneck. Don’t assume higher frequency always means better performance.
**Common Error:** More cache equals faster performance.
**Solution:** Cache size doesn’t always improve performance. In some cases, disabling cache can be faster. Consider cache behavior and loop structures carefully.
**Common Error:** The memory interface timing settings are fine as default.
**Solution:** Default settings are conservative. Adjusting parameters like bus frequency and wait states can improve performance. Sometimes lowering the frequency improves overall efficiency.
**Common Error:** DMA is always faster than software.
**Solution:** True DMA is fast, but embedded versions may require setup overhead. For small data transfers, software might be more efficient. Use DMA only for large blocks.
**Common Error:** Two CPUs will double processing power.
**Solution:** Adding more CPUs requires careful coordination. It's not always a straightforward 1+1=2 scenario. Proper design is crucial to maximize efficiency.
**Mistake 4: Low Power Design**
**Common Error:** Pull-up resistors are harmless.
**Solution:** Some signals don’t need pull-ups. Unnecessary resistors can consume significant power, especially on large buses. Avoid them unless needed.
**Common Error:** We’re using 220V, so power consumption doesn’t matter.
**Solution:** Low power design reduces heat, extends device life, and lowers costs. Even with high voltage, managing power is essential for long-term reliability.
**Common Error:** Small chips don’t consume much power.
**Solution:** Power consumption depends on pin current. A chip may draw more power when driving loads. Always consider real-world usage scenarios.
**Common Error:** Unused I/O ports can be left floating.
**Solution:** Floating I/Os can cause oscillation and increase power consumption. Set unused pins to output mode to avoid issues.
**Common Error:** There are plenty of logic gates left in the FPGA, so I’ll use them.
**Solution:** FPGA power consumption increases with the number of active flip-flops. Minimize usage to save power and improve efficiency.
**Common Error:** I only need OE and WE for memory control.
**Solution:** Chip select (CS) should be used to minimize power consumption. Reducing CS pulse width can further improve efficiency.
**Common Error:** Power savings are a hardware concern only.
**Solution:** Software plays a big role in power management. Optimizing access patterns, using internal caches, and handling interrupts efficiently can significantly reduce power usage.
**Common Error:** Overshoot is always a problem.
**Solution:** Some overshoot is acceptable, especially for TTL or LVDS signals. Matching is not always necessary unless the overshoot is extreme.
[Image: http://i.bosscdn.com/blog/o4/YB/AF/qtxWSAO8N-AAB2hp6C2j8510.png]
**Mistake 5: Signal Integrity**
**Common Error:** Simulation proves everything is fine.
**Solution:** Simulations aren’t perfect. Real-world conditions, such as crosstalk, can cause unexpected issues. Always leave room for margin and test thoroughly.
**Common Error:** More decoupling capacitors mean better power.
**Solution:** Too many capacitors can increase cost and complicate layout. Focus on selecting the right capacitors and placing them correctly, following the chip manufacturer’s guidelines.
**Common Error:** Steeper edges are always better.
**Solution:** Steeper edges generate more high-frequency energy, increasing interference and radiation. Use low-speed components when possible to maintain signal integrity.
**Common Error:** Matching is too complicated.
**Solution:** Signal matching is important when transmission time exceeds transition time. Impedance mismatches can cause reflections, especially in high-speed designs. Keep signal paths simple and avoid branches or vias.
**Common Error:** A 100MHz data bus is high-speed, but the clock is only 8kHz, so it’s safe.
**Solution:** The clock edge is critical for sampling. Even if the clock frequency is low, the edge transition time must be controlled to ensure reliable data capture.
I believe many junior engineers have made similar mistakes during their early projects. If you’ve had similar experiences, share them and help others avoid the same pitfalls. What low-level or serious mistakes have you made? Let’s discuss and learn together!
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