Dual Extreme Low Power Detector Circuit Diagram

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Dual extreme low power detector circuit

The figure shows the circuit diagram of the dual-limit low-power detector. The detector uses a three operational amplifier in the L144 and a CD4011 CMOS NAND gate to form a very low power voltage monitor. If the input voltage Vin is higher than Vhigh or lower than Vlow the output will be logic "high". If the input is within this limit, the output is logic "low". The 1MΩ resistors R1, R2, R3, and R4 turn the bipolar wobble placed within 10V into a wobble within 0~10V to be compatible with ground-referenced CMOS logic.